Canvas is a free graphical DSP design tool that gives access to custom FPGA designs, specially suited for prototyping and users without prior knowledge on HDL languages or FPGA architectures.
In short, a Canvas project consists of a DSP drawing, which is sent to a remote server for automatic VHDL generation, synthesis and implementation. The configuration and loading of the generated output products onto the host FPGA (Redpitaya STEMLab 125) is performed through an intuitive graphical user interface (GUI).
The graphical design tool is based on a add-on package for LTspice, a free electronic circuit simulator. Preconfigured modules such as adders, multipliers, delay blocks, comparators, sample and hold amplifiers, configurable constants… are wired together and connected to the input and output ports .
GUI – Server manager
The GUI includes a Server Manager which handles the connection to a remote server for converting the generated graphical design into parsed NET files and synthesizable VHDL code. It also handles the remote synthesis and implementation, returning only the output products (bitstream and log files).
Outsourcing synthesis and implementation strongly reduces the computational requirements on the user side. Furthermore, the GUI is PyQt5 based (Python 2/3 compatible) and is platform independent: it has been tested for Windows, Linux and Mac OS.
GUI – FPGA manager
The GUI also includes a FPGA manager, which handles the configuration of the host FPGA as well as the loading of bitstream and constants. The configuration and loading is achieved over SSH (ethernet connection) and can be dynamically changed while the host FPGA is operating. This allows to tune the designed DSP circuits in realtime. The FPGA manager also configures the boot behaviour of the FPGA. In this way, bitstream and constants can be automatically reloaded after a power failure.
This project is based on the Red Pitaya STEMLab board, which is a low-cost open-source FPGA development platform. The core of the board is a Xilinx Zynq7010 SoC, consisting of a FPGA interconnected with a dual core ARM processor. Canvas uses SSH to communicate with the processor, which forwards the bitstream and the defined constants to the FPGA. Following I/O capabilities of the Red Pitaya STEMLab board are used:
- 8 digital inputs (3.3V)
- 8 digital outputs (3.3V)
- 8 onboard LEDs
- 2x 125Msamples/s ADC (10/14 bit, depending on board)
- 2x 125Msamples/s DAC (10/14 bit, depending on board)