Canvas

Canvas is a free graphical DSP design tool that gives access to custom FPGA designs, specially suited for prototyping and users without prior knowledge on HDL languages or FPGA architectures.

In short, a Canvas project consists of a DSP drawing, which is sent to a remote server for automatic VHDL generation, synthesis and implementation. The configuration and loading of the generated output products onto the host FPGA (Redpitaya STEMLab 125) is performed through an intuitive graphical user interface (GUI).

Functional Description

LTspice package

The graphical design tool is based on a add-on package for LTspice, a free electronic circuit simulator. Preconfigured modules such as adders, multipliers, delay blocks, comparators, sample and hold amplifiers, configurable constants… are wired together and connected to the input and output ports .

LTspice design. The upper schematic corresponds to a variable offset adder (RF output= RF input + offset) The lower schematic is a counter logic used to blink a LED.

GUI – Server manager

The GUI includes a Server Manager which handles the connection to a remote server for converting the generated graphical design into parsed NET files and synthesizable VHDL code. It also handles the remote synthesis and implementation, returning only the output products (bitstream and log files).

Outsourcing synthesis and implementation strongly reduces the computational requirements on the user side. Furthermore, the GUI is PyQt5 based (Python 2/3 compatible) and is platform independent: it has been tested for Windows, Linux and Mac OS.

Server manager. Screenshot of the server manager (part of the Canvas GUI). It sends the graphical design to the remotes server, which returns parsed NET and synthesizable VHDL files. Thereafter, the corresponding bitstream is generated on a remote server.

GUI – FPGA manager

The GUI also includes a FPGA manager, which handles the configuration of the host FPGA as well as the loading of bitstream and constants. The configuration and loading is achieved over SSH (ethernet connection) and can be dynamically changed while the host FPGA is operating. This allows to tune the designed DSP circuits in realtime. The FPGA manager also configures the boot behaviour of the FPGA. In this way, bitstream and constants can be automatically reloaded after a power failure.

FPGA manager. Screenshot of the FPGA manager (part of the Canvas GUI). It configures over SSH the host FPGA and uploads the generated bitstream and constants. The constant are dynamically configurable allowing rapid tuning of the DSP design.

FPGA

This project is based on the Red Pitaya STEMLab board, which is a low-cost open-source FPGA development platform. The core of the board is a Xilinx Zynq7010 SoC, consisting of a FPGA interconnected with a dual core ARM processor. Canvas uses SSH to communicate with the processor, which forwards the bitstream and the defined constants to the FPGA. Following I/O capabilities of the Red Pitaya STEMLab board are used:

  • 8 digital inputs (3.3V)
  • 8 digital outputs (3.3V)
  • 8 onboard LEDs
  • 2x 125Msamples/s ADC (10/14 bit, depending on board)
  • 2x 125Msamples/s DAC (10/14 bit, depending on board)
Red Pitaya STEMLab (see here). System on a chip (FPGA + microprocessor) routed to digital input/output/LED pins as well 2xADC and 2xDAC, operating at 125 Msamples/s and resolution of 10-14 bits.

Download, Documentation and First Steps

Download (Github)
Documentation and First Steps (Wiki)

7 Replies to “Canvas”

  1. Hello,

    first: absolut great job what you do!!!!!
    2 questions: Is there any possibility to get an output of a 32 bit value to the memory via a DMA transfer?
    Second: Any possibility to get an access to the filters provided by the Xilinx system? I want to build a simple LockIn-amplifier and need for this a lowpass filter?
    And perhaps third question? Can we share our design files anywhere???
    best regards
    Rainer

  2. Hi,

    What a great piece of software! Since I am a newbie to DSP’s, it has made the Red Pitaya so much more accessible and useful for me. Most of my work (for particle accelerators) is in the audio freq range (1kHz-20kHz). Is there any way to add a clock input to the x32_delayVariable? I would like to make FIR filters. Either that or some way of slowing down the clock.
    Thanks for your work!!!

    1. Hi Dave,
      I am glad to hear that the Canvas environment is helpful 🙂 The x32_delayVariable block runs at 125 MHz (like all the other modules) and this can not be changed within Canvas. But you can concatenate multiple of them to achieve longer delays.
      Woukd this help?
      Cheers,
      Pau

      1. Hi Pau,
        I have been trying the x32_delayVariable block with no success. I have been able to run a bunch of different projects with no problem but when I try to use the x32_delayVariable, the Vivado server returns and error.

        Status SYNTH/IMPL ERROR Please check .log files (Zynq_7010 directory).

        Except the Zynq_7010 directory is not created.
        I made a very simple project that has an ADC into the delay block with a DAC out of the delay block along with the required constants. Here is the NET_parsed.net output:

        x32_dac1_0 N000 x32_dac1
        x32_delayVariable_0 N001 N002 N003 N000 x32_delayVariable
        x32_adc1_0 N001 x32_adc1
        x32_const_0 N002 x32_const
        x1_const_0 N003 x1_const

        Am I doing something wrong?
        Dave

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